Some types of memory devices, such as magnetic memories, may experience inherent random errors during operation. These errors are expected and can be corrected during operation. In many cases, an error rate sufficiently high to exhibit errors within less than a second of operation without the use of correction may be corrected during operation with a resulting error rate that is sufficiently low to guarantee months or years of continuous error free operation. For this reason, testing of memory devices to guarantee an acceptable error rate during operation is performed with correction disabled. Since error correction typically requires additional memory cells to store parity information, the testing with correction disabled may require a special mode of operation to access all memory cells. In addition, the circuitry performing the correction must be verified during testing, therefore, testing of at least a portion of the memory must be performed in a second mode of operation with error correction enabled.
When testing magnetic memory devices, the number of correctable errors that occur may be important in determining the viability of the specific device. However, some test systems or services may classify a device as passing or failing based on the existence of a single error and are not easily configured to count or classify devices based on the number and types of errors that occur without adding significant time and cost.